Partitioning and Mapping Communication Graphs on a Modular Reconfigurable Parallel Architecture

A reconfigurable parallel architecture whose interconnection topology can be dynamically modified in order to match the communication characteristics of a given algorithm provides flexibility for efficient execution of various applications. But, due to communication links switching devices design constraints, connecting a large number of processors on a dynamically programmable interconnection structure, leads to the design of a modular interconnection structure. The validation of such a modular reconfigurable interconnection network is based on the demonstration of its ability to support any application coded as communicating sequential processes. This demonstration leads to the mapping problem of any partitionable communicating processes graph on the defined architecture, taking into account communication constraints of the modular and reconfigurable interconnection network. This paper presents results obtained in the context of a research project named MODULOR which objectives were the design and the realization of a massively parallel reconfigurable computer, as well as of the software tools needed for developing applications that efficiently use reconfiguration potentialities of the architecture. 1ּModular reconfigurable parallel architecture context Main problems encountered in the design of a reconfigurable processor network architecture are due to the programmable interconnection topology needed for the connection of a large number of processors [2, 3, 7, 8]. The connection of all the communication links of all the processors on a single crossbar switch is often impossible. A larger interconnection network can be obtained by cascading smaller switching elements, but as the number of elementary crossbar switches increases, it becomes costly and difficult to realize and to program, moreover communication time between processors is directly linked to the number of stages needed to build this interconnection network. Main characteristic of MODULOR architecture is to benefit, as far as possible, from communications locality in order to take into account switching elements size constraints and to minimize communication times as well as interconnection network's complexity. A module allows the connection of a limited number of processors on a first level of communication network, but a second level of interconnection switches is needed for the design of a multimodule architecture [2, 3]. A module is based on the connection of a number N of processors compatible with available crossbar switches characteristics. A first assumption consists in the decomposition of the intra-module interconnection structure into L parts (where L is the number of available communication links per processor). All the links having the same serial number are connected to the same crossbar switch: with this assumption the complexity of each switching element can be divided by the number L of links of each processor. The multimodule architecture needs another communication level between modules. A second assumption deals with the way of connecting communication links of the M modules to the intermodule interconnection structure. Only S ports are reserved on each crossbar switch of a module for communication between modules. It means that each module has L*S external links connected to the second level of crossbar switches. Main characteristics of the logical structure of MODULOR architecture are described on Fig.1.